The data acquisition system to test and characterise the pixel detector modules of the CMS inner tracker for the High Luminosity upgrade of LHC

The LHC will be upgraded to the High Luminosity LHC (HL-LHC) in the coming years to reach an instantaneous luminosity as high as $7.5\times10^{34}$~cm$^{-2}$~s$^{-1}$. This will allow the ATLAS and CMS experiments to collect an integrated luminosity up to $4000$~fb$^{-1}$ during the HL-LHC projected lifetime of ten years, hence increasing the discovery potential of both experiments. To ensure excellent performance despite an average pileup of $200$, the CMS detector is going to be significantly upgraded. The new Inner Tracker has $\times6$ smaller pixels, resulting in about $2$ billions channel, which is unprecedented. The front-end chip features a data readout speed of $1.28$~Gbps, and a downlink for clock, trigger, and commands of $160$~Mbps. The communication between the front-end and the back-end electronics occurs through an optical link based on a custom Low-power Gigabit Transceiver which sends data at $10.24$ and $2.56$~Gbps on the uplink and downlink, respectively. A dedicated data acquisition system, written in C++ and based on a custom micro Data, Trigger, and Control board, equipped with a Xilinx Kintex 7 FPGA, was developed to fully test and characterize the pixel modules. The system architecture and its capabilities are presented in this document.