Etude et mise en œuvre de cellules résistantes aux radiations dans le cadre de l'évolution du détecteur à pixels d'ATLAS en technologie CMOS 65 nm

The 65 nm CMOS technology is a promising technology for the pixel readout chips at HL-LHC in terms of high integration density. The RD53 collaboration was established to develop next generation of pixel readout chips needed by ATLAS and CMS at the HL-LHC, and requiring extreme rate and radiation tolerance. A first 65 nm demonstrator chip (RD53A) has been submitted during the summer 2017. The innermost parts of the new pixel detector will integrate a fluence of about 2.10$^{16}$ n/cm$^{2}$ (1 MeV neutron equivalent) and about 1 GRad Total Ionizing Dose (TID) for 10 years of exploitation. In this work, irradiation studies were done and are presented in order to estimate the TID tolerance of the 65 nm process, and fix some design rules to ensure good functionality in these aggressive operating conditions. Also , in order to optimize the immunity of latches against Single Event Upsets (SEU), various SEU-tolerant structures were designed in the 65 nm technology. This work presents these structures, the tests done at heavy ion beam facilities or under proton irradiations, and shows the level of improvement reached comparing to a standard latch architecture.