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Monolithic pixel detector study for the ATLAS tracker at High Luminosity LHC
A major upgrade to the Large Hadron Collider (LHC), scheduled for 2024 will be brought to the machine so as to extend its discovery potential. This PhD is part of the ATLAS program and aims at studying a new monolithic technology in the framework of the design of an upgraded ATLAS inner tracker. Thi...
Autor principal: | |
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Lenguaje: | eng |
Publicado: |
2022
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/2799821 |
Sumario: | A major upgrade to the Large Hadron Collider (LHC), scheduled for 2024 will be brought to the machine so as to extend its discovery potential. This PhD is part of the ATLAS program and aims at studying a new monolithic technology in the framework of the design of an upgraded ATLAS inner tracker. This new type of sensor is based on a HV/HR CMOS technology, which would potentially offer lower material budget (reduction of multiple scattering), reduced pixel pitch (increased precision for track reconstruction) and lower cost (a particularly important point for an approx. 10 m2 detector) with respect to the traditional hybrid pixel detector concept. Various prototypes have been developed using different HV/HR CMOS technologies from several industrial partners, within the ATLAS HV/HR collaboration, for instance Global Foundry (GF) BCDlite 130 nm and LFoundry (LF) 150 nm. In order to understand the electric behavior and the detection capabilities of these technologies, 3D Technology Computer Aided Design (TCAD) simulations have been performed to extract the depletion zone profile, the breakdown voltage, the leakage current as well as the capacitance of the prototypes. 3D transient simulations were also done in order to investigate the charge collection efficiency and charge sharing of the HV/HR CMOS pixels. For high resistivity substrate prototypes, a 2D guard-ring implementation was as well simulated. In order to explore the sensor performance degradation after irradiation, both Non-Ionizing Energy Loss (NIEL) and Total Ionizing Dose (TID) effects were taken into account when performing the above mentioned simulations. Temperature effects were also introduced in the DC simulations to understand the sensor behavior in a low temperature environment. I have also participated in the test setup developments for the HV/HR CMOS prototypes. My main contributions concerned the modifications of the FPGA firmware and writing of test scripts using C++ and python. I have organized and participated in the laboratory characterizations for AMS 180 nm, GF 130 nm and LF 150 nm prototypes at CPPM, as well as in multiple test sessions of the devices under irradiation at CERN, either at the 24 GeV Proton Synchrotron irradiation center or at a high dose rate X-ray irradiation facility, to study the effects of NIEL and TID on the prototypes. The preamplifier linearity and signalto-noise ratio were measured by using external test injections. The threshold tuning of the pixel matrix could be realized by using the monitor signal func6 tion of the discriminator. A main focus was the investigation of the irradiation hardness for both the electronics and the charge collection sensor. TID effect on the electronics could be performed by characterization of the pre-amplifier, discriminator and the overall analog acquisition chain : Amplitude measurement, threshold and noise evolution with respect to radiation, Single Event Upset rate, etc. . . NIEL effects on silicon were investigated by measuring the counting rate evolution with radiation, leakage current, 55Fe or 90Sr spectra, etc... The possibility of direct communication between the HV/HR CMOS sensor and the FE-I4 (the present readout IC of the innermost ATLAS pixel layer -IBL-) through simple gluing and capacitive coupling was also demonstrated, as well as the concept of sub-pixel encoding using weighted discriminator output in the HV/HR sensor followed by decoding in the FE-I4. The occupancy and time-walk of several prototypes were also measured through the FE-I4. Questions concerning the nonuniformity of the thickness of the epoxy glue used for the capacitive coupling between the sensor and the FE-I4 were also addressed in this way. Beyond participating in the study of the HV/HR CMOS sensors, I have also contributed to calibration procedures of a diagnostic section of the FE-I4 called Generic Analog-to-Digital Converter (GADC) and performed the necessary corresponding measurements. I have developed a compact GUI to visualize the calibration results based on ROOT and extracted calibration constants for all the GADC of all IBL modules. This data is now part of the reference tables used for the IBL layer currently installed in the center of ATLAS. |
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