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Study of low power front-ends for hybrid pixel detectors with sub-ns time tagging
Power consumption is always a concern in the design of readout chips for hybrid pixel detectors. The Timepix3 chip is capable of dealing with up to 80 Mhits/cm$^2$/sec and tagging each hit within a time bin of 1.56 ns. At full speed the Timepix3 chip will consume 1.3 W. We consider how to reduce pow...
| Autores principales: | , , , , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2019
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/14/01/c01024 http://cds.cern.ch/record/2816644 |