Study, implementation and testing of radiation tolerant design for testability solutions for CMS OT FE ASICs

The MPA and SSA development is approaching the production phase with an approximate volume of more than 200k ASICs, corresponding to 1200 wafers. The limited manufacturing yield requires testing strategies able to identify defective units and guarantee the correct functionality of the tracker modules. This contribution presents innovative methods to replace the currently used functional tests for the digital part of the ASICs, showing limited testing accuracy and long testing time. The proposed solution exploits the concept of structural test and new testing algorithms such as Automatic Test Pattern Generation (ATPG) for general digital logic and March for memory elements. Design for Testability (DFT) hardware is integrated on chip to test SRAM memories, peripheral logic and MPA pixel array, providing internal control and observation points for the implementation of the those algorithms. Particular attention is given to power increase, timing and placement impact as well as radiation tolerance of the introduced circuitry, which must be fully transparent during the normal operation of the chip. A faster and more accurate testing approach is presented, from design methodology to implementation choices and silicon results, for a reliable and cost effective testing procedure.