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The front-end electronics upgrade of the CMS ECAL barrel

The barrel part of the CMS electromagnetic calorimeter (ECAL) consists of 61200 PbWO$_4$ crystals coupled to avalanche photodiodes (APDs). A decrease of the ECAL operating temperature from 18$^{\circ}$ C to 9$^{\circ}$ C is needed to mitigate the increase in APD noise from radiation-induced dark cur...

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Detalles Bibliográficos
Autor principal: Cossio, Fabio
Lenguaje:eng
Publicado: 2022
Materias:
Acceso en línea:https://dx.doi.org/10.1016/j.nima.2022.167798
http://cds.cern.ch/record/2825516
Descripción
Sumario:The barrel part of the CMS electromagnetic calorimeter (ECAL) consists of 61200 PbWO$_4$ crystals coupled to avalanche photodiodes (APDs). A decrease of the ECAL operating temperature from 18$^{\circ}$ C to 9$^{\circ}$ C is needed to mitigate the increase in APD noise from radiation-induced dark current in the conditions of the high luminosity upgrade of the LHC. Moreover, a full re-design of the front-end electronics has been undertaken in order to deal with the increase of pileup events and to improve the rejection of anomalous signals generated from direct interaction with the APDs. The VFE (very front-end) card will be equipped with two new ASICs: a fast trans-impedance amplifier named CATIA as well as a data conversion and compression ASIC named LiTE-DTU. The VFE will interface with the radiation tolerant LpGBT transceiver and the VTRx+ optical board, while trigger primitive generation will be moved off-detector to FPGA-based processors. The CATIA ASIC has a single input and two differential outputs with different gains in order to have better resolution for low energy signals. CATIA is designed in commercial CMOS 130 nm technology and can be controlled via an I2C interface. The LiTE-DTU ASIC embeds two 12-bit 160 MS/s ADCs, a sample selection logic, a lossless compression digital logic, and a 1.28 Gb/s serializer that will directly interface with the LpGBT e-links. LiTE-DTU is designed in commercial CMOS 65 nm technology. It embeds a PLL for the generation of the low jitter 1.28 GHz clock required by the ADCs and the serializer. Both ASICs have been extensively tested in lab and beam tests. This new system has been verified to fulfill the requirements of the experiment in terms of performance and radiation tolerance. The ASICs are now in the pre-production phase.