Radiation-Tolerant All-Digital Clock Generators for High Energy Physics

The main focus of the presented research is the development and experimental study of radiation-tolerant clock generation circuits intended for applications in high energy physics (HEP). Clock synthesis and the synchronization of systems on the scale of large experimental detectors is an important aspect of their successful implementation and a necessity for achieving their anticipated performance. Developments in this area to increase radiation tolerance and performance are motivated by emerging requirements for clock generation and distribution. The thesis reviews the requirements of existing and emerging systems with regards to radiation-tolerant clock generation. To characterize clock generation circuits and adequately assess their conformity with the identified requirements in radiation tests, a number of methods and instrumentation setups are developed and characterized. The presented approaches combine aspects of digital programmable logic, analog circuit design and and digital signal processing concepts. To address design challenges in deep submicron CMOS nodes, the design of radiation-tolerant all-digital PLL and CDR circuits is explored in this thesis. These circuits promise opportunities to improve the radiation tolerance of clock generators, and hence this thesis devises the design of a radiation-tolerant ADPLL/CDR circuit compatible with requirements of high energy physics (HEP) electronics. Using radiation testing, the sensitivity of the circuits is studied and mitigation strategies for identified limitations are discussed. Three such ADPLL/CDR circuits are developed and tested in the form of macro blocks targeting applications in frontend ASICs for high energy physics. The circuits demonstrate jitter performance, power efficiency and radiation tolerance comparable to or better than currently used conventional PLL circuits. As a final aspect, the improved testing instrumentation and methodology developed within this thesis is applied to uncover a previously unrecognized radiation sensitivity in a conventional, radiation-hardened clock generator circuit. An integrated planar on-chip inductor is experimentally identified as responsible for this sensitivity. Irradiation tests are performed to study and characterize the nature of this sensitivity. The results suggest that energy deposition, likely within dielectric materials surrounding the inductor wiring, alters the inductor's terminal impedance. This stimulates frequency errors with long recovery times in the oscillator. The manifestation of this effect in HEP radiation environments is studied using proton irradiation, where a mitigation strategy is experimentally validated. A reduction of the impact of this sensitivity is demonstrated. To help conclusively identifying the underlying mechanism responsible for the sensitivity within the inductor itself, further research opportunities are suggested.