Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

The High-Luminosity Large Hadron Collider (HL-LHC) will deliver more than ten times the integrated luminosity of the previous runs 1-3 combined. Meeting higher throughput requirements poses new challenges to the Trigger and Data Acquisition (TDAQ) systems of the LHC experiments. In the framework of the ATLAS experiment’s Phase-II Upgrade, new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 $\mu s$-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, called Global Common Module (GCM). GCM is an Advanced Telecommunications Computing Architecture front board. A matching rear-transition module (RTM), called Generic RTM (GRM) was also developed to mitigate the risks deriving from complex design and power management. GRM features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the Front-End Link eXchange (FELIX) subsystem and trigger processors thought optical links, for readout and control. Additionally, GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This summary presents the GRM hardware design and the testing of its key functionalities.