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Radiation studies performed on the High Luminosity ATLAS TileCal link Daughterboard
The new electronics of the ATLAS TileCal for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring SFPs+ COTS, CERN GBTx ASICs, ProASIC FPGAs and Kintex Ultrascale FPGAs. The design minimizes single point...
Autores principales: | , , , , |
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Lenguaje: | eng |
Publicado: |
2022
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/2835896 |
Sumario: | The new electronics of the ATLAS TileCal for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring SFPs+ COTS, CERN GBTx ASICs, ProASIC FPGAs and Kintex Ultrascale FPGAs. The design minimizes single points of failure and and mitigates and radiation damage by means of a double-redundant scheme, Triple Mode Redundancy, Xilinx Soft Error Mitigation IP, CRC/FEC for link data transfer, and SEL protection circuitries. We present an updated summary of the TID, NIEL and SEE qualification tests, and performance studies of the Daughterboard revision 6 design. |
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