Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 $\mu s$-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). GRM, which was developed to mitigate the risks deriving from complex design and power management of GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25. 8 Gb/s transceiver links, for readout and control. Additionally, GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This article proceeds from the TWEPP 2022 conference and presents the GRM hardware design and the testing of its key functionalities.