Quality Control Testing of the HCC ASIC for the HL-LHC ATLAS ITk Strip Detector

The high-luminosity upgrade to the LHC requires a new silicon-strip charged-particle tracking detector for ATLAS. The HCC (Hybrid Controller Chip) is one of three new radiation-tolerant ASICs for this subsystem. As the interface to multiple binary readout ASICs for the strip detector, the HCC buffers and forwards control signals and trigger and readout requests to them, and serializes their output at 640 MHz. All HCCs undergo a suite of tests to verify their analog and digital functionality, and large statistics of performance with various operational parameters are collected. Yields of HCC ASICs exceed the 90\% required for production.