The AM08 Associative Memory ASIC Design, Architecture and Evaluation methodology

The Associative Memory (AM) ASIC reached its version 8 in 2020 when it was submitted for fabrication. The AM08 has all the functionalities of the final chip, AM0, which was planned for the ATLAS Experiment’s Hardware Track Trigger(HTT) system, at the High-Luminosity Large Hadron Collider(HL-LHC) at CERN. It is made in a 28nm CMOS technology with 10 metal layers and comes in a 15 × 15 FCBGA package. Being a digital chip with a full-custom CAM cell design that can store 12,000 patterns (16 bit × 8 words per pattern), and can achieve 6.25 x 1012 comparisons per second. The Design and Architecture of the chip is presented in this paper. Additionally we discuss the behavioral simulations that run and also the generation of the test vectors purposed for industrial and in-house testing, in VCD and STIL file formats. The laboratory test-benches both for the bare-die chips and the packaged ones are also presented, including the related test-boards. Finally, we discuss the preliminary Power measurements and compare these with the post-layout simulations.