Characterization Studies of a 65nm Radiation-Tolerant Pixel Readout Chip for the CMS Outer Tracker

The Large Hadron Collider (LHC) is the largest accelerator laboratory in the world and is operated by CERN, an international organization dedicated to particle physics research. To fully utilize its physics potential, the High-Luminosity upgrade (HL-LHC) aims to increase the instantaneous luminosity of the accelerator by a factor of 5 to 10. The consequent increases in collision rate, particle track density and radiation dose call for an extensive upgrade of the particle tracking system ("silicon tracker") of the general-purpose CMS detector. The increase in collision events requires an enhanced discrimination towards interesting events. A new discrimination strategy is introduced to the CMS Outer Tracker, where individual modules correlate signals of two closely-spaced sensor layers to filter for high-momentum particle hits. High energy hits are provided continuously at 40 MHz as coarse tracking information to the detector Level-1 trigger system, which uses the information to decide if the collision event is to be further processed or discarded. The Macro-Pixel ASIC (MPA) and Short-Strip ASIC (SSA) are 65 nm CMOS-technology based silicon detector read out-chips designed to satisfy the heightened performance requirements while implementing a fast on-chip particle momentum discrimination logic. The development of the two chips has progressed towards their final prototypes, respectively named MPA2 and SSA2.1. Extensive testing on various stages, ranging from wafer-level probing, single chip characterization on carrier-boards to total ionizing dose (TID) and single event upsets (SEU) irradiation testing have been conducted. Within the scope of this thesis and regarding its future operation in the CMS Outer Tracker, the performance of the MPA2 was characterized and studied. Probe station tests on a sample size of over 3550 MPA2 chips from 17 wafers show that over 90% of them are fully functional. Chip characterization studies in respect to temperature and radiation indicate a good general functionality and show effectiveness of radiation effect mitigation and low-power techniques used in the design of the chip.