Low-Latency Track Triggering in High-Energy Physics

The Compact Muon Solenoid (CMS) is a general-purpose experiment at the Large Hadron Collider (LHC) designed to study a wide variety of high-energy physics phenomena. It employs a large silicon tracker within a homogeneous 3.8 T magnetic field, which allows the precise measurement of the trajectories, including transverse momentum (pT) and vertex position reconstruction of the charged particles emerging from the LHC collisions. The High Luminosity (HL) upgrade of the LHC in 2025 will increase the simultaneous proton-proton collisions from the current average of 25 to up to 200 every 25 ns. The upgrade will completely replace the silicon tracker with one purposely built to discriminate on-module the charged particles whose pT is larger than 2 GeV, these hits are called `stubs'. The stubs are forwarded to off-detector electronics for real-time track reconstruction under 4 μs of latency. For the first time in any particle physics experiment, the reconstructed tracker primitives will be included in the first-level trigger with the aim of maintaining the trigger rate of CMS below 750 kHz This thesis describes various firmware and hardware developments for a real-time all FPGA-based track finder that employs a regionally segmented and fully time-multiplexed architecture. The Time-multiplexed Track Trigger (TMTT) reconstruction algorithm has four processing stages, two of which were implemented in Hardware Description Language (HDL) by the author and are detailed in this dissertation. Optimizations of such algorithms for increased clock frequency operation and resource utilization optimization are also presented. In addition, the development of specialized hardware utilizing the Advanced Telecommunications Computing Architecture (ATCA) form factor will be presented. The board has sufficient high-speed I/O to be used at the HL CMS tracker off-detector processing system. It implements a novel slow-control solution for ATCA systems by combining the Intelligent Platform Management Controller (IPMC), a Linux slow-control software, and an FPGA for custom slow-control tasks in a single Zynq Ultrascale+ (US+) System-on-Chip (SoC) module.