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20 ps time resolution with a fully-efficient monolithic silicon pixel detector without internal gain layer

A second monolithic silicon pixel prototype was produced forthe MONOLITH project. The ASIC contains a matrix of hexagonal pixelswith 100 μm pitch, readout by a low-noise and very fast SiGe HBTfrontend electronics. Wafers with 50 μm thick epilayer of350 Ωcm resistivity were used to produce a fully de...

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Detalles Bibliográficos
Autores principales: Zambito, S., Milanesio, M., Moretti, T., Paolozzi, L., Munker, M., Cardella, R., Kugathasan, T., Martinelli, F., Picardi, A., Elviretti, M., Rücker, H., Trusch, A., Cadoux, F., Cardarelli, R., Débieux, S., Favre, Y., Fenoglio, C.A., Ferrere, D., Gonzalez-Sevilla, S., Iodice, L., Kotitsa, R., Magliocca, C., Nessi, M., Pizarro-Medina, A., Iglesias, J. Sabater, Saidi, J., Pinto, M. Vicente Barreto, Iacobucci, G.
Lenguaje:eng
Publicado: 2023
Materias:
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/18/03/P03047
http://cds.cern.ch/record/2856524
Descripción
Sumario:A second monolithic silicon pixel prototype was produced forthe MONOLITH project. The ASIC contains a matrix of hexagonal pixelswith 100 μm pitch, readout by a low-noise and very fast SiGe HBTfrontend electronics. Wafers with 50 μm thick epilayer of350 Ωcm resistivity were used to produce a fully depletedsensor. Laboratory and testbeam measurements of the analog channelspresent in the pixel matrix show that the sensor has a 130 V widebias-voltage operation plateau at which the efficiency is 99.8%.Although this prototype does not include an internal gain layer, thedesign optimised for timing of the sensor and the front-endelectronics provides a time resolutions of 20 ps.