Hybridisation and assembly of LGAD devices for the HGTD ATLAS upgrade

The High Luminosity era will present a challenge in terms of the number of simultaneous interactions (pile-up) to the LHC experiments. In order to mitigate the detrimental effect of pile-up on physics performance, ATLAS will install a High Granularity Timing Detector (HGTD) that will provide a time resolution per track of 50 ps during its lifetime. HGTD will be made up of hybrid silicon devices. The sensing technology consists of Low Gain Avalanche Detectors (LGADs), which are segmented into a matrix of 15x15 with 1.3x1.3 mm2 pads. The sensors are bump-bonded to the readout ASIC (ALTIROC), producing the HGTD hybrid. Two hybrids are joined by a single module flexible PCB, defining the HGTD module. In this presentation we will discuss the hybridization process and its quality control, the studies carried out to ensure that the timing performance of the chip is not affected by bump-bonding. The assembly process will be discussed as well as the electrical tests performed on the early module prototypes. Results of thermal cycling tests will be presented.