Modélisation et simulation en boucle fermée des systèmes Beam Wire Scanner du CERN à moteur haute performance basé sur la commande vectorielle par FPGA

A Beam Wire Scanner (BWS) instrument for particle accelerators in the framework of the LHC Injectors Upgrade (LIU) has been developed by the European Organization for Nuclear Research (CERN). The BWS is an electro-mechanical system that uses a Permanent Magnet Synchronous Motor (PMSM) to perform the motion of a carbon wire through particle beams. The interaction of the wire with charged particles generates a secondary particle shower captured by a sensor allowing the reconstruction of transverse beam profiles. The precise movement of the motor requires the control of position, speed and motor currents. The control algorithm (nested closed-loop control with PID) is critical for this instrument and therefore is fully developed in VHDL language running inside a dedicated Field Programmable Gate Array (FPGA) but needs to be compared to a reference design in another language for higher reliability. The thesis objective is to validate the control algorithm at Register Transfer Level (RTL) simulation by developing a test bench in SystemVerilog language compatible with the VHDL workflow of the FPGA. The simulation setup of the testbench requires a model of the plant system (composed of the power stage, electro-mechanical system and sensors) to close the feedback loop. The system plant has already been investigated in previous works and a model exists in Matlab/Simulink language but requires an update and some modifications before conversion to SystemVerilog. The control algorithm under verification is called the Design Under Verification (DUV) and must be compared to a reference model of the controller to check its proper operation. The testbench strategy is to stimulate the DUV and the reference model with the same signals and probe their outputs for analysis. Finally, after the necessary tuning and corrections found on the DUV, the output data showed consistent results between the two implementations assessing the control algorithm in use against the newly developed reference design.