A simulation methodology for verification of transient fault tolerance of ASICs designed for high-energy physics experiments

Transient fault tolerance verification is a crucial step in the design of radiation-tolerant ASICs for high-energy physics experiments. In this paper, we discuss a methodical approach toward the verification of transient fault tolerance of ASICs using industry-standard methodologies and tools. The framework for fault verification includes tools for fault enumeration, fault injection, and running fault campaigns. The framework supports fault verification at various levels of design abstraction from high-level register-transfer model to gate-level netlist. The methodology and framework described in this paper were successfully used to identify SEE vulnerabilities in various ASICs designed at CERN.