Faster FPGA firmware synthesis with hls4ml

<!--HTML-->The hls4ml project is a mature library for deployment of neural networks on FPGAs used by the L1 trigger systems of the LHC experiments. With its support for multiple neural network architectures and FPGAs from multiple vendors, the library has recently seen an increase in adoption among the LHC experiments with multiple projects in various stages of development. To meet the latency constraints of the trigger systems the neural networks need to be compressed and fine-tuned for the target FPGA hardware, requiring multiple time-consuming firmware synthesis runs. To facilitate further rapid prototyping of neural networks with hls4ml in this project we will aim to speed up the synthesis flow. My project is on enhancing the internals of hls4ml to support dividing the neural network into blocks that can be synthesized in parallel and reassembled into the final firmware for deployment on hardware. The result of this work will make hls4ml a more usable library, reduce the development lifecycle and foster adoption by the wider scientific community.