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FPGA Cluster algorithm within CMSSW
This study aims to evaluate the performance of the BRIL clustering algorithm in handling data from a particle detector, with a specific focus on its linearity across varying levels of pileup (concurrent collisions). The algorithm's performance is also compared with an existing High-Level Trigge...
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Lenguaje: | eng |
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2023
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Acceso en línea: | http://cds.cern.ch/record/2871594 |
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author | Bensink, Max Antonius |
author_facet | Bensink, Max Antonius |
author_sort | Bensink, Max Antonius |
collection | CERN |
description | This study aims to evaluate the performance of the BRIL clustering algorithm in handling data from a particle detector, with a specific focus on its linearity across varying levels of pileup (concurrent collisions). The algorithm's performance is also compared with an existing High-Level Trigger (HLT) algorithm. Datasets with varying pileups, from 0.5 to 200, are analysed using ROOT modules. Metrics such as hit maps, mean cluster counts, and cluster sizes are considered. Results indicate that the BRIL algorithm maintains its linearity up to high pileup levels and tends to identify slightly more clusters than the HLT algorithm, likely due to the absence of hit-filtering in BRIL. The study suggests potential improvements such as implementing thresholding and removing single-hit clusters for better computational efficiency. Future work could include a more detailed cluster-to-cluster comparison with HLT and testing the algorithm at extremely high pileups to explore its upper operational limits. |
id | cern-2871594 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2023 |
record_format | invenio |
spelling | cern-28715942023-09-18T18:54:13Zhttp://cds.cern.ch/record/2871594engBensink, Max AntoniusFPGA Cluster algorithm within CMSSWComputing and ComputersThis study aims to evaluate the performance of the BRIL clustering algorithm in handling data from a particle detector, with a specific focus on its linearity across varying levels of pileup (concurrent collisions). The algorithm's performance is also compared with an existing High-Level Trigger (HLT) algorithm. Datasets with varying pileups, from 0.5 to 200, are analysed using ROOT modules. Metrics such as hit maps, mean cluster counts, and cluster sizes are considered. Results indicate that the BRIL algorithm maintains its linearity up to high pileup levels and tends to identify slightly more clusters than the HLT algorithm, likely due to the absence of hit-filtering in BRIL. The study suggests potential improvements such as implementing thresholding and removing single-hit clusters for better computational efficiency. Future work could include a more detailed cluster-to-cluster comparison with HLT and testing the algorithm at extremely high pileups to explore its upper operational limits.CERN-STUDENTS-Note-2023-147oai:cds.cern.ch:28715942023-09-18 |
spellingShingle | Computing and Computers Bensink, Max Antonius FPGA Cluster algorithm within CMSSW |
title | FPGA Cluster algorithm within CMSSW |
title_full | FPGA Cluster algorithm within CMSSW |
title_fullStr | FPGA Cluster algorithm within CMSSW |
title_full_unstemmed | FPGA Cluster algorithm within CMSSW |
title_short | FPGA Cluster algorithm within CMSSW |
title_sort | fpga cluster algorithm within cmssw |
topic | Computing and Computers |
url | http://cds.cern.ch/record/2871594 |
work_keys_str_mv | AT bensinkmaxantonius fpgaclusteralgorithmwithincmssw |