Fast Tracking on Heterogeneous Hardware for the ATLAS Event Filter

The High Luminosity upgrade of the Large Hadron Collider (HL-LHC) will deliver $\mathcal{O}(10)$ times the total integrated luminosity of LHC Runs 1-3 combined. However, this increased rate of proton-proton collisions per bunch crossing (pile-up) also poses significant challenges to the ATLAS Trigger and Data Acquisition System (TDAQ). In order to meet the physics goals and realize the full potential of the HL-LHC, the TDAQ system must be able to quickly execute track and vertex reconstruction in this high pile-up environment. The Event Filter (EF) will need to be designed to work at a luminosity of $\mathcal{L} = 7.5 \times 10^{34} \text{ cm}^{-2}\text{s}^{-1}$, with a maximum input rate of 1 MHz and output rate of 10 kHz. Industry trends show a shift toward the usage of heterogeneous systems - systems which integrate multiple types of computational units (GPUs, FPGAs, ASICS, etc.) - which can achieve higher performance with lower power consumption and lower latency than CPU-only systems. Heterogeneous computing systems prove to be a compelling option for a new EF design, which will be responsible for executing sophisticated track reconstruction algorithms in the ATLAS TDAQ system.