Data Preparation And Optimization For Real Time Track Reconstruction On The ATLAS HTT PRM Board

Custom hardware boards for pattern recognition have been developed for the fast reconstruction of charged particle tracks at the ATLAS experiment for the High-Luminosity Large Hadron Colider (HL-LHC) upgrade. The Pattern Recognition Mezzanine (PRM), part of the Hardware Tracking for the Trigger (HTT) system, is one of the boards where track reconstruction is being performed using linearized algorithms in an Intel Stratix 10MX FPGA. The input of the PRM is clustered data from the ATLAS Inner Tracker (ITk) detector. Given the clustered information, the PRM FPGA encodes Superstrip IDs (SSIDs). The SSIDs are a coarser representation of the clustered information which is used for the pattern recognition. Before being further processed by the PRM, the clustered data are sorted per their SSID. A scalable sorting algorithm has been implemented for the fast sorting, taking advantage of the FPGA architecture allowing adjustments for achieving balance between resource utilization and performance. This presentation summarises the PRM board, its firmware design and its challenges. It focuses on the data preparation step, discusses its implementation and reports on tests done with simulated data.