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A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

Detalles Bibliográficos
Autores principales: Santos, D M, Dow, S F, Levi, M E
Lenguaje:eng
Publicado: 1995
Materias:
Acceso en línea:http://cds.cern.ch/record/298697
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author Santos, D M
Dow, S F
Levi, M E
author_facet Santos, D M
Dow, S F
Levi, M E
author_sort Santos, D M
collection CERN
id cern-298697
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 1995
record_format invenio
spelling cern-2986972019-09-30T06:29:59Zhttp://cds.cern.ch/record/298697engSantos, D MDow, S FLevi, M EA CMOS delay locked loop and sub-nanosecond time-to-digital converter chipDetectors and Experimental TechniquesLBL-38040oai:cds.cern.ch:2986971995
spellingShingle Detectors and Experimental Techniques
Santos, D M
Dow, S F
Levi, M E
A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
title A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
title_full A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
title_fullStr A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
title_full_unstemmed A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
title_short A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
title_sort cmos delay locked loop and sub-nanosecond time-to-digital converter chip
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/298697
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AT dowsf acmosdelaylockedloopandsubnanosecondtimetodigitalconverterchip
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