Cargando…
A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
Autores principales: | Santos, D M, Dow, S F, Levi, M E |
---|---|
Lenguaje: | eng |
Publicado: |
1995
|
Materias: | |
Acceso en línea: | http://cds.cern.ch/record/298697 |
Ejemplares similares
-
Monolithic CMOS sensors for sub-nanosecond timing
por: Kugathasan, Thanushan, et al.
Publicado: (2020) -
A high-resolution time-to-digital converter based on an array of delay locked loops
por: Mota, M, et al.
Publicado: (1997) -
Performance of the FASTPIX Sub-Nanosecond CMOS Pixel Sensor Demonstrator
por: Braach, Justus, et al.
Publicado: (2022) -
A multi-channel time-to-digital converter chip for drift chamber readout
por: Santos, D M, et al.
Publicado: (1995) -
On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)
por: Sun, Q, et al.
Publicado: (2009)