Cargando…
RISC Architecture Microprocessor Farm for offline analysis
Autores principales: | De Barros, C, Mendes, M, Miranda, M, Nigri, A, Paiva, E, Santoro, A F S, Schulze, B, Silva, C, Valois, R, Areti, H, Biel, J, Cook, A, Deppe, J, Edel, M, Fischler, M, Gaines, I, Gao, M, Haynes, W B, Husby, D, Isely, M, Nash, T, Zmuda, T |
---|---|
Lenguaje: | eng |
Publicado: |
CERN
1992
|
Materias: | |
Acceso en línea: | https://dx.doi.org/10.5170/CERN-1992-007.467 http://cds.cern.ch/record/400969 |
Ejemplares similares
-
Microprocessor architectures: RISC, CISC and DSP
por: Heath, Steve
Publicado: (1995) -
A Practitioner's guide to Risc microprocessor architecture
por: Stakem, Patrick H.
Publicado: (1996) -
Microprocessor-based data acquisition systems for HERA experiments
por: Haynes, W J
Publicado: (1989) -
RISC without RISK?: an overview of current RISC computers in use in HEP batch
por: Jarp, S
Publicado: (1992) -
Validity and reliability of the German versions of the CD-RISC-10 and CD-RISC-2
por: Wollny, Anna Irena, et al.
Publicado: (2021)