Cargando…
A 4-channels rad-hard delay generator ASIC with 1-ns minimum time step for LHC experiments
Autores principales: | Toifl, Thomas H, Vari, R |
---|---|
Lenguaje: | eng |
Publicado: |
1998
|
Materias: | |
Acceso en línea: | http://cds.cern.ch/record/405081 |
Ejemplares similares
-
A mixed signal data receiver/clock synchronizer ASIC for analog front end chips in LHC experiments
por: Posch, C, et al.
Publicado: (1998) -
A radiation-hard 80-MHz clock and data recovery circuit for LHC
por: Toifl, Thomas H, et al.
Publicado: (1998) -
Rad hard and rad tolerant IC's developed to satisfy the extreme space and LHC requirements
por: Durand, G, et al.
Publicado: (1990) -
Delay25 an ASIC for timing adjustment in LHC
por: Furtado, Hugo
Publicado: (2005) -
SCTA - A Rad-Hard BiCMOS Analogue Readout ASIC for the ATLAS Semiconductor Tracker
por: Anghinolfi, Francis, et al.
Publicado: (1996)