Deep submicron CMOS technologies for the LHC experiments

The harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demons...

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Detalles Bibliográficos
Autores principales: Jarron, Pierre, Anelli, G, Calin, T, Cosculluela, J, Campbell, M, Delmastro, M, Faccio, F, Giraldo, A, Heijne, Erik H M, Kloukinas, Kostas C, Letheren, M F, Nicolaidis, M, Moreira, P, Paccagnella, A, Marchioro, A, Snoeys, W, Velazco, R
Lenguaje:eng
Publicado: 1999
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1016/S0920-5632(99)00615-5
http://cds.cern.ch/record/428707
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author Jarron, Pierre
Anelli, G
Calin, T
Cosculluela, J
Campbell, M
Delmastro, M
Faccio, F
Giraldo, A
Heijne, Erik H M
Kloukinas, Kostas C
Letheren, M F
Nicolaidis, M
Moreira, P
Paccagnella, A
Marchioro, A
Snoeys, W
Velazco, R
author_facet Jarron, Pierre
Anelli, G
Calin, T
Cosculluela, J
Campbell, M
Delmastro, M
Faccio, F
Giraldo, A
Heijne, Erik H M
Kloukinas, Kostas C
Letheren, M F
Nicolaidis, M
Moreira, P
Paccagnella, A
Marchioro, A
Snoeys, W
Velazco, R
author_sort Jarron, Pierre
collection CERN
description The harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demonstrated on transistor and circuit level, and design implications are discussed. A model for the effective W/L of an enclosed transistor is given, a radiation- tolerant standard cell library is presented, and single event effects are discussed. (22 refs).
id cern-428707
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 1999
record_format invenio
spelling cern-4287072019-09-30T06:29:59Zdoi:10.1016/S0920-5632(99)00615-5http://cds.cern.ch/record/428707engJarron, PierreAnelli, GCalin, TCosculluela, JCampbell, MDelmastro, MFaccio, FGiraldo, AHeijne, Erik H MKloukinas, Kostas CLetheren, M FNicolaidis, MMoreira, PPaccagnella, AMarchioro, ASnoeys, WVelazco, RDeep submicron CMOS technologies for the LHC experimentsDetectors and Experimental TechniquesThe harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demonstrated on transistor and circuit level, and design implications are discussed. A model for the effective W/L of an enclosed transistor is given, a radiation- tolerant standard cell library is presented, and single event effects are discussed. (22 refs).oai:cds.cern.ch:4287071999
spellingShingle Detectors and Experimental Techniques
Jarron, Pierre
Anelli, G
Calin, T
Cosculluela, J
Campbell, M
Delmastro, M
Faccio, F
Giraldo, A
Heijne, Erik H M
Kloukinas, Kostas C
Letheren, M F
Nicolaidis, M
Moreira, P
Paccagnella, A
Marchioro, A
Snoeys, W
Velazco, R
Deep submicron CMOS technologies for the LHC experiments
title Deep submicron CMOS technologies for the LHC experiments
title_full Deep submicron CMOS technologies for the LHC experiments
title_fullStr Deep submicron CMOS technologies for the LHC experiments
title_full_unstemmed Deep submicron CMOS technologies for the LHC experiments
title_short Deep submicron CMOS technologies for the LHC experiments
title_sort deep submicron cmos technologies for the lhc experiments
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1016/S0920-5632(99)00615-5
http://cds.cern.ch/record/428707
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