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Pulling the trigger on LHC electronics

The conditions at CERN's Large Hadron Collider pose severe challenges for the designers and builders of front-end, trigger and data acquisition electronics. A recent workshop reviewed the encouraging progress so far and discussed what remains to be done. The LHC experiments have addressed level...

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Autor principal: CERN. Geneva
Lenguaje:eng
Publicado: 2001
Materias:
Acceso en línea:http://cds.cern.ch/record/516250
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author CERN. Geneva
author_facet CERN. Geneva
author_sort CERN. Geneva
collection CERN
description The conditions at CERN's Large Hadron Collider pose severe challenges for the designers and builders of front-end, trigger and data acquisition electronics. A recent workshop reviewed the encouraging progress so far and discussed what remains to be done. The LHC experiments have addressed level one trigger systems with a variety of high-speed hardware. The CMS Calorimeter Level One Regional Trigger uses 160 MHz logic boards plugged into the front and back of a custom backplane, which provides point-to-point links between the cards. Much of the processing in this system is performed by five types of 160 MHz digital applications-specific integrated circuits designed using Vitesse submicron high-integration gallium arsenide gate array technology. The LHC experiments make extensive use of field programmable gate arrays (FPGAs). These offer programmable reconfigurable logic, which has the flexibility that trigger designers need to be able to alter algorithms so that they can follow the physics and detector performance more closely as luminosity and beam conditions change. During the past decade there has been a remarkable improvement in FPGA speed and capacity, while the price has dropped. The enhanced performance of these devices is resulting in improved level one trigger designs. Another important industrial development is the advent of high band-width telecoms switches. These devices allow hundreds of buffers of LHC front-end read-out electronics to be connected to the hundreds of computer processing nodes that must analyse the data. The greater the bandwidth of these switches, the more data can be brought directly to the processing nodes for detailed analysis. The option to have an increasing proportion of commodity hardware in the read-out network and data processing enables more easily scalable and supportable designs, which can be augmented with additional straightfoward purchases as more processing power is needed. Overall, the LEE workshop in Cracow provided an excellent opportunity for the international community of physicists and engineers from the four LHC experiments to review their work in preparing the electronics for constructing working detectors in 2005. (0 refs).
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institution Organización Europea para la Investigación Nuclear
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spelling cern-5162502019-09-30T06:29:59Zhttp://cds.cern.ch/record/516250engCERN. GenevaPulling the trigger on LHC electronicsDetectors and Experimental TechniquesThe conditions at CERN's Large Hadron Collider pose severe challenges for the designers and builders of front-end, trigger and data acquisition electronics. A recent workshop reviewed the encouraging progress so far and discussed what remains to be done. The LHC experiments have addressed level one trigger systems with a variety of high-speed hardware. The CMS Calorimeter Level One Regional Trigger uses 160 MHz logic boards plugged into the front and back of a custom backplane, which provides point-to-point links between the cards. Much of the processing in this system is performed by five types of 160 MHz digital applications-specific integrated circuits designed using Vitesse submicron high-integration gallium arsenide gate array technology. The LHC experiments make extensive use of field programmable gate arrays (FPGAs). These offer programmable reconfigurable logic, which has the flexibility that trigger designers need to be able to alter algorithms so that they can follow the physics and detector performance more closely as luminosity and beam conditions change. During the past decade there has been a remarkable improvement in FPGA speed and capacity, while the price has dropped. The enhanced performance of these devices is resulting in improved level one trigger designs. Another important industrial development is the advent of high band-width telecoms switches. These devices allow hundreds of buffers of LHC front-end read-out electronics to be connected to the hundreds of computer processing nodes that must analyse the data. The greater the bandwidth of these switches, the more data can be brought directly to the processing nodes for detailed analysis. The option to have an increasing proportion of commodity hardware in the read-out network and data processing enables more easily scalable and supportable designs, which can be augmented with additional straightfoward purchases as more processing power is needed. Overall, the LEE workshop in Cracow provided an excellent opportunity for the international community of physicists and engineers from the four LHC experiments to review their work in preparing the electronics for constructing working detectors in 2005. (0 refs).oai:cds.cern.ch:5162502001
spellingShingle Detectors and Experimental Techniques
CERN. Geneva
Pulling the trigger on LHC electronics
title Pulling the trigger on LHC electronics
title_full Pulling the trigger on LHC electronics
title_fullStr Pulling the trigger on LHC electronics
title_full_unstemmed Pulling the trigger on LHC electronics
title_short Pulling the trigger on LHC electronics
title_sort pulling the trigger on lhc electronics
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/516250
work_keys_str_mv AT cerngeneva pullingthetriggeronlhcelectronics