Development and a SEU Test of a TDC LSI for the ATLAS Muon Detector

A new TDC LSI (AMT-2) for the ATLAS Muon detector has been developed. The AMT-2 chip is a successor of the previous prototype chip (AMT-1). The design of the chip was polished up for aiming mass production of 20,000 chips in year 2002. Especially, power consumption of the chip was reduced to less than half of the previous chip by introducing newly developed LVDS receivers. The AMT-2 was processed in a 0.3 mu m CMOS Gate-Array technology. It achieved 300 ps timing resolution and includes several data buffers, trigger matching circuit, JTAG interface and so on. First SEU test by using a proton beam was recently performed. Although the test results are very preliminary at present stage, we get very low SEU rate safely used in ATLAS environment. (7 refs).