A novel simulation and verification approach in an ASIC design process

We have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Veri...

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Detalles Bibliográficos
Autores principales: Husmann, D, Keller, M, Mahboubi, K, Pfeiffer, U, Schumacher, C
Lenguaje:eng
Publicado: 2000
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/560363
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author Husmann, D
Keller, M
Mahboubi, K
Pfeiffer, U
Schumacher, C
author_facet Husmann, D
Keller, M
Mahboubi, K
Pfeiffer, U
Schumacher, C
author_sort Husmann, D
collection CERN
description We have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Verilog HDL (hardware description language) and embedded in a system wide analog and digital simulation or implemented algorithms. We present here our design environment and experience that we gained from the design process. (10 refs).
id cern-560363
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2000
record_format invenio
spelling cern-5603632019-09-30T06:29:59Zhttp://cds.cern.ch/record/560363engHusmann, DKeller, MMahboubi, KPfeiffer, USchumacher, CA novel simulation and verification approach in an ASIC design processDetectors and Experimental TechniquesWe have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Verilog HDL (hardware description language) and embedded in a system wide analog and digital simulation or implemented algorithms. We present here our design environment and experience that we gained from the design process. (10 refs).oai:cds.cern.ch:5603632000
spellingShingle Detectors and Experimental Techniques
Husmann, D
Keller, M
Mahboubi, K
Pfeiffer, U
Schumacher, C
A novel simulation and verification approach in an ASIC design process
title A novel simulation and verification approach in an ASIC design process
title_full A novel simulation and verification approach in an ASIC design process
title_fullStr A novel simulation and verification approach in an ASIC design process
title_full_unstemmed A novel simulation and verification approach in an ASIC design process
title_short A novel simulation and verification approach in an ASIC design process
title_sort novel simulation and verification approach in an asic design process
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/560363
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