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A novel simulation and verification approach in an ASIC design process
We have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Veri...
| Autores principales: | , , , , |
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| Lenguaje: | eng |
| Publicado: |
2000
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/560363 |