An MWPC readout chip for high rate environment

An ASIC has been fabricated in order to readout data from an MWPC that is installed in high rate environment. 16 channels and an ancillary control circuit are packed in a chip, and a channel consists of LVDS Receiver and 100-stage shift register array for delay. A hit data from the chamber is once input in the shift register array, and is just output from it when the trigger signal is set. If a channel contains a signal during a gate followed by the trigger, the channel is regarded to contain a hit. The primary purpose to construct the chip is for test beam and cosmic ray test of ATLAS thin gap chambers (TGC), which are used for the muon trigger signal generation. The architecture of the ASIC is so simple and uidependent from the specific readout scheme of ATLAS TGC. It will be found that the ASIC is adopted easily for any readout scheme of MWPC like detector. 3 Refs.