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Third level trigger of the DIRAC experiment
A fast and complete programmable high level trigger processor for the DIRAC experiment at CERN was designed and arranged based on state-of- art field programmable gate array (FPGA) technology. The implemented logic was created from Monte Carlo simulation results and further checked with real experim...
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| Lenguaje: | eng |
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2002
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| Acceso en línea: | https://dx.doi.org/10.1016/S0168-9002(01)01414-0 http://cds.cern.ch/record/588652 |