Submicron CMOS technologies for high energy physics and space applications

The radiation environment present in some of today's High-Energy Physics (HEP) experiments and in space has a detrimental influence on the integrated circuits working in these environments. Special technologies, called radiation hardened, have been used in the past to prevent the radiation-induced degradation. In the last decades, the market of these special technologies has undergone a considerable shrinkage, rendering them less reliably available and far more expensive than today's mainstream technologies. An alternative approach is to use a deep submicron CMOS technology. The most sensitive part to radiation effects in a MOS transistor is the gate oxide. One way to reduce the effects of ionizing radiation in the gate oxide is to reduce its thickness, which is a natural trend in modern technologies. Submicron CMOS technologies seem therefore a good candidate for implementing radiation-hardened integrated circuits using a commercial, inexpensive technology. Nevertheless, a certain number of radiation-induced problems still need to be solved. These problems can be addressed with special layout rules and circuit architectures, as explained in the paper. The effectiveness of this approach has been demonstrated on several circuits which will be used for the experiments of the Large Hadron Collider (LHC), the new accelerator presently under construction at CERN. (24 refs).