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The fast tracker processor for hadronic collider triggers
Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stor...
| Autores principales: | , , , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2000
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/619212 |