Pattern Recognition in the TRT for the ATLAS B-Physics Trigger

The current B-physics trigger strategy in LVL2 starts with a scan of the full volume of the TRT to reconstruct all tracks with pT > 0.5 GeV. Since the detector volume to be analysed is 100 times larger than a typical RoI, and the pT range of the track search extends down to 0.5 GeV, an additional factor of 10 in processing power is required in comparison with the high-pT TRT feature extraction algorithm which has a 5 GeV threshold. At low luminosity, the full scan will be performed as part of the B-physics trigger with a frequency of 9 kHz. Taking into account all these factors, the full scan at low luminosity will require 100 times more computing power than the RoI-guided scan at design luminosity. It is the most challenging of all LVL2 algorithms in terms of computing power and bandwidth requirements. A very fast and therefore simple algorithm is thus essential, independent of the hardware realisation. This paper presents a TRT track reconstruction algorithm which is based on a Hough Transform using a look-up table (LUT). The pattern recognition is ideally suited for an FPGA implementation, whereas the track fit is more suited for implementation on general-purpose processors. The use of a general-purpose processor with FPGA co-processor allows an implementation which best matches the characteristics of the algorithmic parts to the strengths of both hardware components. In this case the execution time for the entire process, pattern recognition plus fit, is reduced by a factor of 20. All stages of the algorithm are implemented in C++. In addition the pattern recognition steps, apart from the fit, are also implemented in VHDL (standardised Hardware Description Language) for FPGAs (Field Programmable Gate Arrays). For the algorithm development and quality studies, the C++ version was used. The FPGA implementation was compared with the C++ version. Identical behaviour and an improvement in speed was demonstrated.