High Speed Backplane links for the L1 Trigger Cluster Processor Module

The design of the Cluster Processor Crate within the ATLAS L1 Calorimeter trigger requires a large number of high speed data links between modules.Data signals are sent at 160Mb/s across the backplane to reduce the number of module inter-connections and the pin count of onboard processing devices, while covering the largest possible area of the calorimeter. A transmission scheme is needed to reliably carry these signals across a backplane through module connectors and into the processing devices. This report describes the evaluation of CMOS and GTL transmission schemes which can be used for direct connection to either ASIC or FPGA devices.