Event loss rates and readout chips

98-57 The LHCb experiment aims at a deadtimeless readout of B­events at a primary bunch crossing rate of 40 MHz. In order to achieve this goal, information from all events must be stored in a pipeline with latency matched to the time needed for the Level 0 trigger decision. Accepted events, which constitute only a small fraction of the total sample, are stored in a fifo of a certain depth and read out with a fixed clock rate. The fifo, also referred to as multi­event or derandomizing buffer, is needed in order to even out statistical fluctuations in the trigger rate. Apart from the length of the pipeline, which determines the maximum latency of the chip, the crucial parameter characterizing a readout chip is the fraction of triggers lost due to limitations of the chip's architecture. This note describes how the different design parameters and operation conditions determine the chip's performance.