APV logic simulations

The amount of data in the CMS inner tracker system at the LHC interaction rate is so large that it cannot be read out at each bunch crossing. A pipeline memory is then needed to store the data at the front-end level until a Level 1 Trigger accept signal marks the interesting data which will then be read out. Due to the random arrival of triggers with a maximum average rate of 100kHz a queue may develop in the pipeline which in the end can become full and cause errors. Some triggers must then be vetoed. In the present version of the chip to be used in the Tracker read-out, the APV6, the memory ( storage, marking of interesting data, read-out and clearing) is governed by a very complex embedded logic: precise predictions concerning the inefficiency due to vetoing the triggers can be done only by means of computer simulation. This document is mainly intended to give an extensive descriptionof the logic and to present the results obtained by running an updated version of the simulation. A further generation of the chip, the APV25 ( based on silicon submicron technology) is under development: its digital logic will be simplified with respect to the APV6. Results on the efficiency expected from the APV25 are also shown.