APV6 Pipeline Emulations

The data volume from the CMS inner tracker is large enough that data cannot be read out for every bunch crossing, so data are stored in the front end readout chips until a first level trigger signal is received, after which the interesting data are read out. This will reduce the data rate from 40 MHz to 100 kHz. For the silicon microstrips, the data are read out using the APV6 chip which holds the data in an analogue pipeline for up to 3.2 us. Up to 6 events may be stored in the pipeline at any one time, and data are read out asynchronously. In any system where data arrives with a random distribution in time, a finite sized memory can become full, causing data to be lost. Because of the complex nature of the APV6 pipeline logic, a true estimate of the proportion of data which will be lost can only be achieved by running a computer emulation of the pipeline logic, with a poisson distribu tion of trigger signals. The emulation has also been modified to study the effect of other possible logic designs.