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The L0(muon) processor
99-008 In this note we review the Marseille implementation for the L0(muon) processor. We describe the data flow, hardware implementation, synchronization issue as well as our first ideas on debugging and monitoring procedure. We also present the performance of the proposed architecture with an esti...
| Autores principales: | , , , , , |
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| Lenguaje: | eng |
| Publicado: |
1999
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/691579 |
| Sumario: | 99-008 In this note we review the Marseille implementation for the L0(muon) processor. We describe the data flow, hardware implementation, synchronization issue as well as our first ideas on debugging and monitoring procedure. We also present the performance of the proposed architecture with an estimate of its cost. |
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