GiGabit Ethernet mezzanines for DAQ and Trigger links of LHCb

The LHCb experiment uses IEEE 802.ab (GiGabit ethernet) technology for the data transport and readout network layer between the L1 data buffers and the CPU farm. The common way to interface the L1 buffers in LHCb to the physical layers of GiGabitEthernet (GBE) is specified in this document. The SPI-3 industry standard is used as a narrow, FiFo-like interface which can be easily implemented in the FPGAs of the L1 boards. The SPI-3 protocol on the mezzanine cards is handled by commercial chips. Up to 4 bidirectional GBE channels can be implemented on a 149*74 mm mezzanine of stackheight 11 mm. These are interfaced through one 150 pin, high-speed connector which is defined here as LHCb standard.