GiGabit Ethernet mezzanines for DAQ and Trigger links of LHCb

The LHCb experiment uses IEEE 802.ab (GiGabit ethernet) technology for the data transport and readout network layer between the L1 data buffers and the CPU farm. The common way to interface the L1 buffers in LHCb to the physical layers of GiGabitEthernet (GBE) is specified in this document. The SPI-...

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Detalles Bibliográficos
Autores principales: Müller, H, Bal, F, Guirao, A
Lenguaje:eng
Publicado: 2003
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/691591
_version_ 1780902021385158656
author Müller, H
Bal, F
Guirao, A
author_facet Müller, H
Bal, F
Guirao, A
author_sort Müller, H
collection CERN
description The LHCb experiment uses IEEE 802.ab (GiGabit ethernet) technology for the data transport and readout network layer between the L1 data buffers and the CPU farm. The common way to interface the L1 buffers in LHCb to the physical layers of GiGabitEthernet (GBE) is specified in this document. The SPI-3 industry standard is used as a narrow, FiFo-like interface which can be easily implemented in the FPGAs of the L1 boards. The SPI-3 protocol on the mezzanine cards is handled by commercial chips. Up to 4 bidirectional GBE channels can be implemented on a 149*74 mm mezzanine of stackheight 11 mm. These are interfaced through one 150 pin, high-speed connector which is defined here as LHCb standard.
id cern-691591
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2003
record_format invenio
spelling cern-6915912019-09-30T06:29:59Zhttp://cds.cern.ch/record/691591engMüller, HBal, FGuirao, AGiGabit Ethernet mezzanines for DAQ and Trigger links of LHCbDetectors and Experimental TechniquesThe LHCb experiment uses IEEE 802.ab (GiGabit ethernet) technology for the data transport and readout network layer between the L1 data buffers and the CPU farm. The common way to interface the L1 buffers in LHCb to the physical layers of GiGabitEthernet (GBE) is specified in this document. The SPI-3 industry standard is used as a narrow, FiFo-like interface which can be easily implemented in the FPGAs of the L1 boards. The SPI-3 protocol on the mezzanine cards is handled by commercial chips. Up to 4 bidirectional GBE channels can be implemented on a 149*74 mm mezzanine of stackheight 11 mm. These are interfaced through one 150 pin, high-speed connector which is defined here as LHCb standard.LHCb-2003-021oai:cds.cern.ch:6915912003-04-07
spellingShingle Detectors and Experimental Techniques
Müller, H
Bal, F
Guirao, A
GiGabit Ethernet mezzanines for DAQ and Trigger links of LHCb
title GiGabit Ethernet mezzanines for DAQ and Trigger links of LHCb
title_full GiGabit Ethernet mezzanines for DAQ and Trigger links of LHCb
title_fullStr GiGabit Ethernet mezzanines for DAQ and Trigger links of LHCb
title_full_unstemmed GiGabit Ethernet mezzanines for DAQ and Trigger links of LHCb
title_short GiGabit Ethernet mezzanines for DAQ and Trigger links of LHCb
title_sort gigabit ethernet mezzanines for daq and trigger links of lhcb
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/691591
work_keys_str_mv AT mullerh gigabitethernetmezzaninesfordaqandtriggerlinksoflhcb
AT balf gigabitethernetmezzaninesfordaqandtriggerlinksoflhcb
AT guiraoa gigabitethernetmezzaninesfordaqandtriggerlinksoflhcb

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