Cargando…
Specification of the muon trigger processing board
In this note we establish the specification of the processing board for the Level zero muon trigger.
Autores principales: | Aslanides, Elie, Cachemiche, J P, Dinkespiler, B, Derue, F, Duval, P Y, Le Gac, R, Leroy, O, Liotard, P L, Menouni, M, Potheau, R, Tsaregorodtsev, A Yu |
---|---|
Lenguaje: | eng |
Publicado: |
2002
|
Materias: | |
Acceso en línea: | http://cds.cern.ch/record/691627 |
Ejemplares similares
-
A realistic algorithm for the level 0 muon trigger
por: Aslanides, Elie, et al.
Publicado: (2003) -
A synchronous architecture for the L0 muon trigger
por: Aslanides, Elie, et al.
Publicado: (2001) -
High speed parallel optical links for the LHCb muon trigger
por: Aslanides, Elie, et al.
Publicado: (2003) -
High speed ribbon optical link for the level 0 muon trigger
por: Aslanides, Elie, et al.
Publicado: (2003) -
Map of the trigger sectors for the muon detector
por: Aslanides, Elie, et al.
Publicado: (2003)