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Readout Unit-FPGA version for link multipexers, DAQ and VELO trigger
The FPGA-based Readout Unit (RU) was designed as entry stage to the readout networks of the LHCb data acquisition and L1-VELO topology trigger systems. The RU performs subevent building from up to 16 custom S-link inputs towards a commercial readout network via a PCI interface card. For output to cu...
| Autores principales: | , , , |
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| Lenguaje: | eng |
| Publicado: |
2003
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/691650 |