The Beetle Reference Manual

This paper details the port de nitions, electrical speci cations, modes of operation and programming sequences of the 128 channel readout chip Beetle . The chip is developed for the LHCb experiment and ful lls the requirements of the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detector in case of multianode photomultiplier readout. It integrates 128 channels with low-noise charge-sensitive preampli ers and shapers. The risetime of the shaped pulse is 25 ns with a 30% remainder of the peak voltage after 25 ns. A comparator per channel with con gurable polarity provides a binary signal. Four adjacent comparator channels are being ORed and brought o chip via LVDS ports. Either the shaper or comparator output is sampled with the LHC-bunch-crossing frequency of 40 MHz into an analogue pipeline with a programmable latency of max. 160 sampling intervalls and an integrated derandomizing bu er of 16 stages. For analog readout data is multiplexed with up to 40 MHz onto 1 or 4 ports. A binary readout mode operates at up to 80 MHz output rate on two ports. Current drivers bring the serialized data o chip. The chip can accept trigger rates of up to 1 MHz to perform a deadtimeless readout within 900 ns per sample. For testability and calibration purposes, a charge injector with adjustable pulse height is implemented. The bias settings and various other parameters can be controlled via a standard I 2 C-interface.