An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC

The Beam Synchronous Timing system (BST) will be used around the LHC and its injector, the SPS, to broadcast timing meassages and synchronize actions with the beam in different receivers. To achieve beam synchronization, the BST Master card encodes messages using the bunch clock, with a nominal valu...

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Detalles Bibliográficos
Autores principales: Ballester, F J, Domínguez, D, Gras, J J, Lewis, J, Savioz, J J, Serrano, J
Lenguaje:eng
Publicado: 2003
Materias:
Accelerators and Storage Rings
Acceso en línea:http://cds.cern.ch/record/693176

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