PLL Usage in the General Machine Timing System for the LHC

Analogue PLLs have been successfully used for decades to recover clocks and clean the jitter introduced by transmission media. Nevertheless the design parameters are hard to change once the PCB has been mounted. Digital PLLs overcome this problem. They can be either completely digital, substituting...

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Detalles Bibliográficos
Autores principales: Alvarez-Sanchez, P, Domínguez, D, King, Q, Lewis, J, Serrano, J, Todd, B
Lenguaje:eng
Publicado: 2003
Materias:
Accelerators and Storage Rings
Acceso en línea:http://cds.cern.ch/record/693179
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author Alvarez-Sanchez, P
Domínguez, D
King, Q
Lewis, J
Serrano, J
Todd, B
author_facet Alvarez-Sanchez, P
Domínguez, D
King, Q
Lewis, J
Serrano, J
Todd, B
author_sort Alvarez-Sanchez, P
collection CERN
description Analogue PLLs have been successfully used for decades to recover clocks and clean the jitter introduced by transmission media. Nevertheless the design parameters are hard to change once the PCB has been mounted. Digital PLLs overcome this problem. They can be either completely digital, substituting the VCO by a Numeric Oscillator, or they can keep a VCXO in case a low jitter is needed. This paper describes both configurations and gives lab results for the latter. This architecture will be used in every General Machine Timing reveiver card for the LHC.
id cern-693179
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2003
record_format invenio
spelling cern-6931792022-08-17T13:35:37Zhttp://cds.cern.ch/record/693179engAlvarez-Sanchez, PDomínguez, DKing, QLewis, JSerrano, JTodd, BPLL Usage in the General Machine Timing System for the LHCAccelerators and Storage RingsAnalogue PLLs have been successfully used for decades to recover clocks and clean the jitter introduced by transmission media. Nevertheless the design parameters are hard to change once the PCB has been mounted. Digital PLLs overcome this problem. They can be either completely digital, substituting the VCO by a Numeric Oscillator, or they can keep a VCXO in case a low jitter is needed. This paper describes both configurations and gives lab results for the latter. This architecture will be used in every General Machine Timing reveiver card for the LHC.CERN-AB-2003-114-COoai:cds.cern.ch:6931792003-11-08
spellingShingle Accelerators and Storage Rings
Alvarez-Sanchez, P
Domínguez, D
King, Q
Lewis, J
Serrano, J
Todd, B
PLL Usage in the General Machine Timing System for the LHC
title PLL Usage in the General Machine Timing System for the LHC
title_full PLL Usage in the General Machine Timing System for the LHC
title_fullStr PLL Usage in the General Machine Timing System for the LHC
title_full_unstemmed PLL Usage in the General Machine Timing System for the LHC
title_short PLL Usage in the General Machine Timing System for the LHC
title_sort pll usage in the general machine timing system for the lhc
topic Accelerators and Storage Rings
url http://cds.cern.ch/record/693179
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AT dominguezd pllusageinthegeneralmachinetimingsystemforthelhc
AT kingq pllusageinthegeneralmachinetimingsystemforthelhc
AT lewisj pllusageinthegeneralmachinetimingsystemforthelhc
AT serranoj pllusageinthegeneralmachinetimingsystemforthelhc
AT toddb pllusageinthegeneralmachinetimingsystemforthelhc

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