Clock generation and distribution for the 130-nm Itanium$^{R}$ 2 processor with 6-MB on-die L3 cache

The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher freq...

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Detalles Bibliográficos
Autores principales: Tam, S, Desai, U N, Limaye, R D
Lenguaje:eng
Publicado: 2004
Materias:
Engineering
Acceso en línea:https://dx.doi.org/10.1109/JSSC.2004.825121
http://cds.cern.ch/record/779431
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author Tam, S
Desai, U N
Limaye, R D
author_facet Tam, S
Desai, U N
Limaye, R D
author_sort Tam, S
collection CERN
description The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.
id cern-779431
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2004
record_format invenio
spelling cern-7794312019-09-30T06:29:59Zdoi:10.1109/JSSC.2004.825121http://cds.cern.ch/record/779431engTam, SDesai, U NLimaye, R DClock generation and distribution for the 130-nm Itanium$^{R}$ 2 processor with 6-MB on-die L3 cacheEngineeringThe clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.oai:cds.cern.ch:7794312004
spellingShingle Engineering
Tam, S
Desai, U N
Limaye, R D
Clock generation and distribution for the 130-nm Itanium$^{R}$ 2 processor with 6-MB on-die L3 cache
title Clock generation and distribution for the 130-nm Itanium$^{R}$ 2 processor with 6-MB on-die L3 cache
title_full Clock generation and distribution for the 130-nm Itanium$^{R}$ 2 processor with 6-MB on-die L3 cache
title_fullStr Clock generation and distribution for the 130-nm Itanium$^{R}$ 2 processor with 6-MB on-die L3 cache
title_full_unstemmed Clock generation and distribution for the 130-nm Itanium$^{R}$ 2 processor with 6-MB on-die L3 cache
title_short Clock generation and distribution for the 130-nm Itanium$^{R}$ 2 processor with 6-MB on-die L3 cache
title_sort clock generation and distribution for the 130-nm itanium$^{r}$ 2 processor with 6-mb on-die l3 cache
topic Engineering
url https://dx.doi.org/10.1109/JSSC.2004.825121
http://cds.cern.ch/record/779431
work_keys_str_mv AT tams clockgenerationanddistributionforthe130nmitaniumr2processorwith6mbondiel3cache
AT desaiun clockgenerationanddistributionforthe130nmitaniumr2processorwith6mbondiel3cache
AT limayerd clockgenerationanddistributionforthe130nmitaniumr2processorwith6mbondiel3cache

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