A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment

The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of t...

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Detalles Bibliográficos
Autores principales: De Robertis, G, Loddo, F, Ranieri, A
Lenguaje:eng
Publicado: 1999
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1016/S0168-9002(99)00470-2
http://cds.cern.ch/record/781165
Descripción
Sumario:The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment.

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